Recapping CCIX at DAC 2017 and TERATEC 2017

By Jeff Defilippi, Arm • August 10, 2017

Accelerators Acronix Arm Cache Coherent Interconnect Cadence DAC Design Automation Conference Jeff Defilippi Members Networking Servers Storage Synopsys Xilinx

Over the past few weeks, ARM participated in several CCIX panels and talks at two conferences, the Design Automation Conference (DAC 2017) held in Austin TX and TERATEC 2017, an HPC forum held in Paris, France. It was a good opportunity to discuss the technical challenges of big data workloads and to discuss how CCIX can address with improve performance and efficiency for acceleration workloads within data center and networking systems. Here’s a quick recap of the events.

While at DAC, I participated in a couple of events. First up was a roundtable moderated by Brian Bailey from SemiconductorEngineering with CCIX members Gaurav Singh (Xilinx), Sachin Dhingra (Cadence), John Koeter (Synopsys), and Kent Orthner (Achronix). We had a very good discussion overviewing the CCIX technology and describing the workloads that benefit from cache coherent, peer-processing. We also discussed how CCIX simplifies software by eliminating run time drivers and interrupt signaling with a shared virtual memory system shared by processors and accelerators.

Later in the week, I presented on the Cadence stage where I not only provided an overview of CCIX, but also highlighted a couple of CCIX IP products, ARM’s CoreLink CMN-600 Coherent Mesh Network and the Cadence CCIX IP. The IP products can be combined by System-on-Chip (SoC) designers to construct a range of CCIX enabled SoCs including high core count servers, smart network or storage devices and any number of accelerators. By leverage existing PCIe infrastructure, the cost and risk of integration CCIX with the IP products is reduced dramatically and allows for dual-mode ports that can configured at boot time to support legacy PCIe hardware or to enable CCIX taking advantage of added bandwidth (up to 25GT/s) and cache coherency.

My colleague Neil Parris then presented at the TERATEC 2017 Interconnect Workshop. Most of the interconnect talks were focused on scale-out, smart networks. These smart network SoCs typically connect to a host processor over PCIe today. As the HPC market drives toward exascale, these smart networks require more bandwidth to support 200 Gigabit Ethernet (and beyond) and require more intelligence off-load capabilities. Neil was able to highlight how the 3x more bandwidth (vs current PCIe Gen3 interfaces), lower latency and shared coherent memory system with CCIX provides a significant performance boost to these smart networks.

The CCIX consortium continues to build momentum with the recent CCIX product announcements and 25Gbps performance demonstration so be on the look-out for more member companies discussing CCIX technology and products at conferences throughout the remainder of the year. Check our news and events page for the latest product announcements, press releases and events. https://www.ccixconsortium.com/news-events-1